Timing system for timing a series of events

ABSTRACT

The invention relates to a timing system designed to count a series of events and the time lapse of the occurance of each event from a starting signal. A plurality of gates control clock pulses which are counted by a number of counter-registers, the number of which depends upon the number of events to be counted. As each event is counted, a different one of the counterregisters is stopped from counting clock pulses thereby recording the lapse time from the starting signal to the occurance of the event.

Unitedv States Pa Mallett et al.

tent 1 451 Feb. 26, 1974 TIMING SYSTEM FOR TIMING A SERIES OF EVENTS [75] Inventors: Paul H. Mallett, Rt. 5, Box 226;

Calvin Pipes, both of Monroe, La.

[73] Assignee: said Mallett, by said Pipes [22] Filed: Jan. 8, 1973 [211 App]. No.: 321,746

52 us. or. 324/186 [5] Int. Cl G04f 9/00, G04f 11/06 [58] Field of Search... 324/186, 181, 178; 235/92 T; t 2731/1022 R [56] References Cited UNITED STATES PATENTS 3,302,007 1/1967 Parkinson 235/92 T SHOT count L GATES PREAM'P SHA PER SHOT COUNTER AU nltal. E SSITGANRATL /7/ l RESET I /J 44 l ggigg RESET T0 RESETS U STItRT CONTROL SIGNAL LINYE 3,594,643 I 7/1971 Hunt 324/1 86 Primary ExaminerAlfred E. Smith Attorney, Agent, or Firm-John E. Vandigriff [57] ABSTRACT The invention relates to a timing system designed to count 21 series of events and the time lapse of the occurance of each event from a starting signal. A plurality of gates control clock pulses which are counted by a number of counter-registers, the number of which depends upon the number of events to be counted. As each event is counted, a different one of the counterregisters is stopped from counting clock pulses thereby recording the lapse time from the starting signal to the occurance of the event.

7 Claims, 5 Drawing Figures o srnsnor SEC REGISTER 3/6 40 2 o I 2ND.SHOT l W 42 REGISTER 3 EC I s I r 32 |ST.SHOT |o 0 REGISTER 3/ sec.

EVENTS FIELD OF THE INVENTION This invention relates to an apparatus for timing aseries of events and more particularly to an apparatus for timing and recording a series of events for subsequent display.

When events to be timed occur in rapid succession in a very short time interval, it is difficult to accurately time each event. A stop watch is useful in timing a single event. Chart recorders can record a series of events and the time between events, but when the total time lapse is only a few seconds or fractions thereof, the ac curacy provided by a chart recorder is not sufficient. The timing apparatus of the present invention is designed to overcome these and other disadvantages of present day timing apparatus.

SUM MARY'OF THE INVENTION This invention is applicable to any situation in which it is desired to measure small time intervals between the occurance of one or more events after a predetermined event. One application of the apparatus is in the training of peace officersin the use of handguns, particularly in the drawing andrapid firing of the handgun.

The apparatus is basicallya digital counter-computer designed to count a series of events and time their occurance from a predetermined event. In utilizing the apparatus in handgun training, the time required to draw a handgun and tire five shots is timed. Each shot is counted and the lapse time of each shot from a starting signal is timed and recorded. In the specific embodiment described below, only the first, second and fifth shots are timed and recorded, however the concept and design of the invention permits counting and recording any number of shots over any time interval.

A more comprehensive understanding of the inven-- tion will be had when considering the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 isa simplified circuit diagram illustrating a timing system constructed according to the present invention;

FIG. 2 is a circuit diagram of the start control and reset circuits of the system illustrated in FIG. 1;

FIG. 3 is a circuit diagram ,of the input preamplifier and pulse shaper of the system illustrated in FIG. 1;

FIG. 4 is acircuit diagram of the register control circuit of the system of FIG. 1; and,

FIG. 5 is a circuit diagram of the first shot register and visual display of the system of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT cords the time for the first, second and fifth shotsv All five shots could be recorded by adding additional counter-registers and related gating circuits similar to those described below.

Operation of the system shown in FIG. 1 is as follows. The reset switch 14 is pressed to ensure that all circuits are made ready to receive the shot count pulses generated in responce to each shot, count the shots, record the time lapse between the start signal and each shot and store the computed time for subsequent display.

After all circuits have been reset to their respective starting conditions, the start button in the start control circuit 13 is pressed generating an audible start signal such as that produced by horn 12. A start control signal in the form of a pulse is also generated andcoupled via the start control signal line 15 to the shot count gates 20, 21 and 22 causing the gates to change states, enabling the clock gates 26, 27 and 28 permitting them to pass pulses from clock 29 to the shot registers 30, 40 and 50. Clock 29 may be, for example, an oscillator which is controlled by a crystal or vibrating reed to generate pulses at the rate of pulses per second. The clock pulses coupled to the counter-registers are counted until the clock gates are disabled by shots or after a predetermined time lapse as hereinafter explained.

The count or timelapse recorded in the counterregister is stored and may be displayed on display devices 32, 42 and 52 any time until the system is reset for the next timing period. The Time stored in any one counter-register may be displayed by rotating selector switch 31 to the desired position for display of the time lapse of the first, second or third shot. The display may be anyone of several types available such as tubes having electrodes in the shape of numerals or devices havingseven segments which may be illuminated to display numerals.

After the start of the timed event, each shot is detected by microphone l0, generating a pulse which is amplified and shaped in pre-amplifier and shaper 11. The pulses, each representing a shot, is coupled to shot counter 17. Shot counter 17 encodes each count into binary form. Such a counter may have, for example, four output lines A, B, C and D. As input pulses are counted, the output signal changes as shown in TABLE 1.

SHOT D c B A TABLE 1 Conventional terminology is used in the description of the circuits of the timing system. A l or H" indicates that an input or output signal is high or at a predetermined voltage level. An 0 orL is low and is a predetermined voltage lever lower that the l From TABLE 1 it may be observed that for the first shot only the A output line is a 1. For the second shot only the B is at 1 but for the fifth shot both output lines A and C are at 1. By connecting the output lines to gates 23, 24 and 25 as illustrated in FIG. 1,

only one gate at a time is affected by each shot. The

output on line D does not change since the highest shot count is five. Therefore, this output line is not used.

When the first shot is counted, gate 25 changes state. Since gate 25 is connected to gate 22, the change of state of gate 25 also causes gate 22 to return to the state it was in prior to receiving the start control signal thus disabling gate 28 preventing the clock pulse from reaching the first shot counter-register 30. Counteri register 30 stops counting since it is no longer receiving clock pulses, thereby recording the time lapse from the start of the time sequence to the time the first shot was fired. Shot two will subsequently stop the counting of the second shot counter-register 40 and the fifth shot will stop the counting of the fifth shot counter-register 50. In the event no shot is fired after a time lapse of be visually displayed by readouts 32, 42 and 52 which display time in l/ 100 second, 1 l second and seconds, respectively. The time recorded in each register may be displayed by rotating switch 31 to one of three positions, position I displaying the time recorded in shot register 1, position 2 displaying the time recorded in shot register 2 and position 3 displaying the time recorded in shot register 5. In the event no shot is fired and the time thereof recorded in its respective register within 3.88 seconds, then the time 3.88 seconds will be displayed for that register.

In the description which follows, various circuits are described in more detail which corresponds to one preferred embodiment of the invention. Reference is made, in some instances, to specific integrated circuit devices which may be used for that particular circuit. Where specific devices are mentioned, they are devices manufactured by one or more semiconductor manufacturers from which detailed specifications may be obtained. Therefore devices mentioned will only be illustrated in block or symbolic form. Where specific device designationsare given, they are by way of example only and other similar devices may'be used which will accomplish the desired circuit function.

FIG. 2 is a more detailed illustration of the start control l3 and reset circuit 14 shown in FIG. 1. Start switch 53 is connected to one input of a two input N AND gate 51 and reset switch 52 is connected to one input of two input NAND gate 50. Gates 50 and 51 are crossed coupled to from a circuit commonly refered to as an R-S NAND latch. The characteristic of such a circuit is that the output changes immediately when there is a change on either of the inputs. when the reset in the drawings may be NAND gates such as found in integrated circuit device SN 7400.

When the start switch 53 is closed, a 0 is applied to gate 51 and a l is generated at its output. This 1 is applied to circuit 56 which maybe, for example, a monostable multivibrator or Schmitt trigger. The application of the l to the input causes an output of 0" which is generated at the output terminal of the device labeled 6. This 0 is applied to the start control signal line 15 which is connected to gates 20, 21 and 22 (FIG. 4).

FIG. 3 illustrates the shot input circuit which includes microphone 10, preamplifier 11a and pulse circuit 1 lb. The shot noise is picked up'by microphone 10, amplitied and shaped. The frequency responce of preamplifier 11a may be such that only a sharp noise such as a shot is amplified and other background noise is filtered out. The amplified shot sound is applied to the pulse shaping circuit which may be, for example, a monostable multivibrator which is triggered by the shot pulse. The pulse thus amplified and shaped is applied to shot counter 17 (FIG. 4).

FIG. 4 illustrates the clock control gates which enable the clock gates permitting the clock pulses to each register-counter and to disable the clock count to each register as each shot is counted. When the start signal is applied to line 15, the start signal is applied to crosscoupled gates 20a, 20b 21a, 21b and 22a, 22b causing each of these gates to change states applying a logic 0 to each of gates 26, 27 and 28. The clock pulse on each of these gates causes the output to go to logic l with each clock pulse. These clock pulses are counted by each of the counter-register circuits.

With the occurrence of the first shot, counter 17 counts, changing the output as indicated in TABLE 1. A logic l appears on output A and is coupled to gate 25, which has both of its inputs tied together. When a logic 1 appears on both of the inputs of gate 25, a logic 0 appears on the output..This causes the crosscoupled gates 20a and 29b to change states applying a logic 1 to one of the inputs of gate 26. The application of this logic l along with the clock pulse to the input of gate 26 generates a logic 0 at its output, therefore effectively blocking the clockpulse and i stopping the count of the first shot counter-register.

Upon receipt of the second shot count, the output of counter 17 changes to reflect the second count, a l appearing on output B and a O on outputs A and C. This l is applied to gate 24 which is coupled to gates 21a and 21b, changing the state of these cross-coupled gates applying a logic I to gate 27 which will block the clock pulse-from passing through gate thereby stopcause a change of state of cross-coupled gates 22a and 22b. Gate 28 is disabled stopping the clock pulse from reaching shot register 5 thereby stopping the count of this register.

FIG. 5 is a detailed circuit of shot register 1. Since shot registers 3 and 5 are identical to shot register 1, both in circuit and in function, a description of only one shot register will be given.

The clock pulse is coupled through gate 26 and gate 33 to counter 35. Counter 35 is a decade counter which will count each clock pulse, resetting itself every tenth count. The output of counter 35 is applied to counter 36 which is also a decade counter. Every tenth clock count will be applied to the input of counter 36. The output of counter 35 is also applied to gate 34 for reasons which will be explained later. Counter 36 will counteach tenth pulse of the clock and every tenth pulse counted will appear on line D. This output is connected to the clock input of a JK flipflop counting circuit.

Flip-flop 37 (also flop 38) is wired to form a T Flip-flop by connecting the JK inputs together-to form a single input and connecting them to a logic 1. A T" flip-flop may be defined as a flip-flop that has only a single data input and a clock input. The output of a T flip-flop will change states with each change in clock pulse. By taking the output of flip-flop 37 and tying it to the clock input of flip-flop 38, a. simple counter is constructed. This counter will count from 0 o 3 and rsrys sath r iv h 299219 of the D output of counter 36 is counted until pulses (i.e., 3 seconds) have been counted. A decade counter could be used in place of the flip-flops 37 and 38 to permit counts higher than three.

ln observing the overall operation of counters 35 and 36 and the countermade up of flip-flops 37 and 38, it may be observed that counter 35 counts each clock pulse thereby counting pulses at the rate of 100 per second. Since counter 35 devides by ten, it supplies only one out of every pulses to counter 36. Counter 36 counts at the rate of 10 per second. Counter '36 also divides the pulses by l0,'thereby producing only one pulse per second so that the counter made up of flipflops 37 and 38 will receive counts at the rate of one per second and will count up to three before it recycles. The output of each of the counter circuits is applied to a decode driver circuit (61,-62 and 63) which drives the display indicators (64, 65 & 66) thereby indicating the count of each of the counters. The display66 which is driven by counter 35 will indicate 1/100 of a cecond. Display 65 will count 1/10 seconds and display 64 will count in seconds, thereby indicating the time lapse from the start of the timing sequence until the count is stopped by a shot.

It was previously mentioned that the counter would automatically stop after a lapse time of 3.88 seconds from the start. This is accomplished as follows. Four input NAND gate 34 has one input connected to the D output of counter 35, one input connected to the D output of counter 36, one input connected to the A output of counter flip-flop 38 and one output connected to output B of flip-flop 37. When each of these three outputs is in a l the state of the cross-coupled gates 33 and 34 will change, blocking the clock pulse preventing its passage through gate 33, thereby stopping the count to the counter-register board in the event that a shot has not previously stopped the count. I should be noted that when each of the above mentioned outputs are at a l, the decimal equivalent is 3.88 seconds. When the D output of counter 35 reaches 1 it will be at an eight count. The same is true for counter 36. When both the A and B outputs of the counter made up of flip-flops 37 and 38 are l a 1 binary three is represented. Therefore when each of the lines is a l the decimal number is 3.88 seconds. At this point the registers are prevented from counting further by the disabling of gate 33, preventing the passage therethrough of the clock pulse in the event that a shot has not stopped the clock pulse prior to this point in time.

Although the invention has been described in regard to a particular specific embodiment, it should be understood numerous changes in the details of the construction may be resorted to without departing from the spirit and the scope of the invention as hereinafter claimed.

We claim:

1. A timing system for timing the happening of a series of one or more sequential events from a starting signal comprising, a clock for generating timing pulses, a plurality of gates through which said timing pulses are passed, a plurality of binary counter-registers which count and store the number of timing pulses received after the start signal, an event counter for receiving a signal representative of an event and generating a different binary encoded signal for each event as it occurs,

each of said different binary encoded signals disabling 3. The timing system according to claim 1, wherein the timing system automatically will cease timing after a predetermined time lapse.

4. The timing system according to claim 1, wherein said gates includes a separate gate for each counterregister which has an input from the clock and the event counter so that when an event occurs, one of the gates is disabled, blocking the clock timing pulses from reaching the counter-register.

5. A timing system for measuring short time intervals of less than one minute between the occurance of a series of one or more sequential events after a predetermined event, comprising, a clock for generating timing pulses, a plurality of counters for counting pulses from said clock, a plurality of first gates through which said timing pulses are passed to said counters, an event counter for receiving a signal representative of an event and generating a signal for each event that is different from the signal generated for the other events, a second plurality of gates connected to said event counter and said first gates, each of which responds to a different one of said signals representative of an event, each of said first gates being disabled when a second gates is connected thereto in response to one of said signals representative of an event and a plurality of counterregisters connected to said counters for recording the time lapse from said predetermined event to the occurance of said one or more events.

6. The apparatus according to claim 5, wherein the time interval during which events occur is less that 5 seconds.

7. The apparatus according to claim 5, wherein the time lapse count stored in the counter-register may be visually displayed. 

1. A timing system for timing the happening of a series of one or more sequential events from a starting signal comprising, a clock for generating timing pulses, a plurality of gates through which said timing pulses are passed, a plurality of binary counter-registers which count and store the number of timing pulses received after the start signal, an event counter for receiving a signal representative of an event and generating a different binary encoded signal for each event as it occurs, each of said different binary encoded signals disabling a different one of said gates to stop a different counter-register from receiving the timing pulses, thereby recording in each counterregister the time lapse, from the starting signal, of the occurance of the event which caused the counter-register to stop counting.
 2. The timing system according to claim 1, wherein the time lapse of each event is displayed in seconds of time.
 3. The timing system according to claim 1, wherein the timing system automatically will cease timing after a predetermined time lapse.
 4. The timing system according to claim 1, wherein said gates includes a separate gate for each counter-register which has an input from the clock and the event counter so that when an event occurs, one of the gates is disabled, blocking the clock timing pulses from reaching the counter-register.
 5. A timing system for measuring short time intervals of less than one minute between the occurance of a series of one or more sequential events after a predetermined event, comprising, a clock for generating timing pulses, a plurality of counters for counting pulses from said clock, a plurality of first gates through which said timing pulses are passed to said counters, an event counter for receiving a signal representative of an event and generating a signal for each event that is different from the signal generated for the other events, a second plurality of gates connected to said event counter and said first gates, each of which responds to a different one of said signals representative of an event, each of said first gates being disabled when a second gates is connected thereto in response to one of said signals representative of an event and a plurality of counter-registers connected to said counters for recording the time lapse from said predetermined event to the occurance of said one or more events.
 6. The apparatus according to claim 5, wherein the time interval during which events occur is less that 5 seconds.
 7. The apparatus according to claim 5, wherein the time lapse count stored in the counter-register may be visually displayed. 